IBM PowerPC 403GCX
EDO DRAM 2-1-1-1 Burst Read Followed by Single Transfer Read
1
2
RAS
3
CAS0
4
CAS1
5
CAS2
6
CAS3
7
Pre-Chg
8
9
10
RAS
11
CAS0
12
Pre-Chg
13
Cycle
SysClk
A6:291
WBE2/A30
WBE3/A31
Row
Addr
Row
Addr
Column
Addr
Col 1
Col 2
Col 3
Col 4
AMuxCAS
R/W
RAS
CAS
DramOE
DramWE
D0
D1
D2
D3
D4
D0:31, DP0:3
Note 2
Error?
?
?
?
?
BusError
Error?
Bank Register Bit Settings
Bus
Width Mux
Ext RAS-to- Refresh Page
First
Burst
Prechg Refresh Refresh
SLF ERM
CAS
Mode
Mode Access Access Cycles
RAS
Rate
Bit 13 Bit 14 Bits Bit 17 Bit 18
15:16
Bit 19
Bit 20
1
Bits
21:22
Bits
23:24
Bit 25
0
Bit 26
Bits
27:30
x
0
10
0
0
0
00
00
1
xxxx
Notes:
1. IOCR[EDO] is set and IOCR[DRC] is cleared.
2. Data is latched with respect to the fall of the internal system clock (duty-cycle corrected).
3. Data parity, if enabled, matches the timing of data bus transfers.
45
IBM [ IBM ]
