IBM PowerPC 403GCX
DRAM 3-2-2-2 Page Mode Write
1
2
3
4
5
6
7
8
9
10 11 12
SysClk
A11:29
Pre-
Charge
RAS
CAS
CAS
CAS
CAS
CAS
CAS
CAS
CAS
Row
Column1
Column2
Column3
Column4
AMuxCAS
R/W
RAS
CAS0:3
DRAMOE
DRAMWE
Data1
Error?
Data2
Error?
Data3
Data4
D0:31
Error?
Error?
BusError
Bank Register Bit Settings
Bus
Width Mux
Ext RAS-to- Refresh Page
First
Burst
Prechg Refresh Refresh
SLF ERM
CAS
Mode
Mode Access Access Cycles
RAS
Rate
Bit 13 Bit 14 Bits Bit 17 Bit 18
15:16
Bit 19
Bit 20
Bits
21:22
Bits
23:24
Bit 25
Bit 26
Bits
27:30
0 or 1
0
xx
x
0
0
1
01
01
0
x
xxxx
Notes:
1. For burst access, the addresses represented by Columns 1 to 4 do not necessarily indicate that they are in incre-
mental address order. Typically, burst access is target word first.
2. If internal mux mode is used, address bits A11:29 represent address bits described in Table 22 on page 37.
3. During internal mux mode access, A6:10 retain their unmultiplexed values.
4. If external mux mode is used, A11:29 are unaffected and do not change between CAS and RAS cycles.
5. If bus width is programmed as byte or half-word, WBE2:3 represent address bits A30:31 regardless of mux mode.
6. WBE0:1 are always ones during DRAM transfers.
7. DRAM read on CAS, IOCR[DRC], and EDO DRAM, IOCR[EDO], modes do not affect writes.
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