H5PS1G43EFR
H5PS1G83EFR
H5PS1G63EFR
-Continued-
DDR2-667
DDR2-800
Symbol
Unit
Notes
Parameter
min
max
min
max
Internal write to read command delay
Internal read to precharge command delay
Exit self refresh to a non-read command
Exit self refresh to a read command
tWTR
tRTP
7.5
7.5
-
7.5
7.5
-
ns
ns
24,32
3,32
32
tXSNR
tXSRD
tRFC + 10
200
tRFC + 10
200
ns
-
-
-
-
nCK
Exit precharge power down to any non-read
command
tXP
2
2
2
2
nCK
nCK
nCK
Exit active power down to read command
tXARD
tXARDS
1
Exit active power down to read command
(Slow exit, Lower power)
7 - AL
8 - AL
1, 2
CKE minimum pulse width
(HIGH and LOW pulse width)
tCKE
3
2
3
2
nCK
nCK
ns
27
16
ODT turn-on delay
ODT turn-on
tAOND
tAON
2
2
tAC(max)
+0.7
tAC(max)
+0.7
tAC(min)
tAC(min)
6,16,40
2tCK(avg)+
tAC(max)+1
tAC(min)
+2
2tCK(avg)+
tAC(max)+1
ODT turn-on(Power-Down mode)
ODT turn-off delay
tAONPD
tAOFD
tAOF
tAC(min)+2
2.5
ns
nCK
ns
2.5
2.5
2.5
17,45
tAC(max)
+0.6
17,43,4
5
ODT turn-off
tAC(min)
tAC(max)+ 0.6
tAC(min)
tAC(min)
+2
2.5tCK(avg)+
tAC(max)+1
tAC(min)
+2
2.5tCK(avg)+
tAC(max)+1
ODT turn-off (Power-Down mode)
tAOFPD
ns
ODT to power down entry latency
ODT power down exit latency
OCD drive mode output delay
tANPD
tAXPD
tOIT
3
8
0
3
8
0
nCK
nCK
ns
12
12
32
15
tIS + tCK
(avg)
+ tIH
Minimum time clocks remains ON after CKE
asynchronously drops LOW
tIS + tCK (avg)
+ tIH
tDelay
ns
Rev. 0.4 / Nov 2008
25
HYNIX [ HYNIX SEMICONDUCTOR ]
