H5PS1G43EFR
H5PS1G83EFR
H5PS1G63EFR
4. Differential data strobe
DDR2 SDRAM pin timings are specified for either single ended mode or differential mode depending on the
setting of the EMR “Enable DQS” mode bit; timing advantages of differential mode are realized in system
design. The method by which the DDR2 SDRAM pin timings are measured is mode dependent. In single
ended mode, timing relationships are measured relative to the rising or falling edges of DQS crossing at VREF.
In differential mode, these timing relationships are measured relative to the crosspoint of DQS and its com-
plement, DQS. This distinction in timing methods is guaranteed by design and characterization. Note that
when differential data strobe mode is disabled via the EMR, the complementary pin, DQS, must be tied exter-
nally to VSS through a 20 Ω to 10 KΩ resistor to insure proper operation.
t
t
DQSL
DQSH
DQS
DQS
DQS/
DQS
t
t
WPST
WPRE
V
(dc)
V
(ac)
IH
IH
DQ
DM
D
D
D
t
D
t
V
(ac)
V
(dc)
IL
IL
t
t
DH
DH
DS
DS
V
(dc)
V
(ac)
IH
IH
DMin
DMin
DMin
(ac)
DMin
(dc)
V
IL
V
IL
Figure -- Data input (write) timing
t
t
CL
CH
CK
CK
CK/CK
DQS
DQS
DQS/DQS
DQ
t
t
RPRE
RPST
Q
Q
Q
Q
t
DQSQmax
t
DQSQmax
t
t
QH
QH
Figure -- Data output (read) timing
5. AC timings are for linear signal transitions. See System Derating for other signal transitions.
6. All voltages referenced to VSS.
7. These parameters guarantee device behavior, but they are not necessarily tested on each device. They
may be guaranteed by device design or tester correlation.
8. Tests for AC timing, IDD, and electrical (AC and DC) characteristics, may be conducted at nominal refer-
ence/supply voltage levels, but the related specifications and device operation are guaranteed for the full
voltage range specified.
Rev. 0.4 / Nov 2008
27
HYNIX [ HYNIX SEMICONDUCTOR ]
