H5PS1G43EFR
H5PS1G83EFR
H5PS1G63EFR
Timing Parameters by Speed Grade (DDR2-400 and DDR2-533)
DDR2-400
DDR2-533
Symbol
Unit
Note
Parameter
min
max
+600
+500
0.55
0.55
-
min
-500
-450
0.45
0.45
max
+500
+450
0.55
0.55
-
DQ output access time from CK/CK
DQS output access time from CK/CK
CK HIGH pulse width
tAC
-600
-500
0.45
0.45
ps
ps
tDQSCK
tCH
tCK
tCK
ps
CK LOW pulse width
tCL
tHP
min(tCL,
tCH)
min(tCL,
tCH)
11,12
15
CK half period
Clock cycle time, CL=x
tCK
5000
150
8000
-
3750
100
8000
-
ps
ps
6,7,8,20
,28
DQ and DM input setup time(differential strobe)
tDS(base)
6,7,8,21
,28
DQ and DM input hold time(differential strobe)
tDH(base)
275
-
225
-
ps
DQ and DM input setup time(single ended strobe)
DQ and DM input hold time(single ended strobe)
tDS(base)
tDH(base)
25
25
-
-
-25
-25
-
-
ps
ps
6,7,8,25
6,7,8,26
Control & Address input pulse width for each
input
tIPW
0.6
-
0.6
-
tCK
DQ and DM input pulse width for each input
Data-out high-impedance time from CK/CK
tDIPW
tHZ
0.35
-
-
0.35
-
-
tCK
ps
tAC max
tAC max
18
18
tLZ
(DQS)
DQS low-impedance time from CK/CK
DQ low-impedance time from CK/CK
tAC min
2*tAC min
-
tAC max
tAC max
350
tAC min
2*tAC min
-
tAC max
tAC max
300
ps
ps
ps
tLZ
(DQ)
18
DQS-DQ skew for DQS and associated DQ
signals
tDQSQ
13
12
DQ hold skew factor
tQHS
tQH
-
tHP - tQHS
WL - 0.25
0.35
0.35
0.2
450
-
tHP - tQHS
WL - 0.25
0.35
0.35
0.2
400
ps
DQ/DQS output hold time from DQS
Write command to first DQS latching transition
DQS input HIGH pulse width
DQS input LOW pulse width
DQS falling edge to CK setup time
DQS falling edge hold time from CK
Mode register set command cycle time
Write preamble
-
-
ps
tDQSS
tDQSH
tDQSL
tDSS
tDSH
tMRD
tWPRE
tWPST
tIS
WL + 0.25
WL + 0.25
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
ps
-
-
-
-
-
-
0.2
-
-
0.2
-
-
2
2
0.35
0.4
-
0.35
0.4
-
Write postamble
0.6
-
0.6
-
10
5,7,9,23
5,7,9,23
19
Address and control input setup time
Address and control input hold time
Read preamble
350
250
tIH
475
-
375
-
ps
tRPRE
tRPST
0.9
1.1
0.6
0.9
1.1
0.6
tCK
tCK
Read postamble
0.4
0.4
19
Active to active command period for 1KB
page size products (x4, x8)
ns
ns
4
tRRD
tRRD
7.5
10
-
-
7.5
10
-
-
Active to active command period for 2KB
page size products (x16)
4
Rev. 0.4 / Nov 2008
22
HYNIX [ HYNIX SEMICONDUCTOR ]
