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H5PS1G83EFR 参数 Datasheet PDF下载

H5PS1G83EFR图片预览
型号: H5PS1G83EFR
PDF下载: 下载PDF文件 查看货源
内容描述: 1GB DDR2 SDRAM [1Gb DDR2 SDRAM]
分类和应用: 动态存储器双倍数据速率
文件页数/大小: 44 页 / 566 K
品牌: HYNIX [ HYNIX SEMICONDUCTOR ]
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H5PS1G43EFR  
H5PS1G83EFR  
H5PS1G63EFR  
tDS, tDH Derating Values for DDR2-400, DDR2-533(ALL units in 'ps', Note 1 applies to entire Table)  
DQS, DQS Single-ended Slew Rate  
1.8 V/ns 1.6 V/ns 1.4 V/ns  
4.0 V/ns  
3.0 V/ns  
2.0 V/ns  
1.2 V/ns  
1.0 V/ns  
0.8 V/ns  
tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH  
2.0 188 188 167 146 125  
63  
42  
0
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43  
1
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1.5 146 167 125 125  
83  
0
81  
-2  
1.0  
0.9  
0.8  
0.7  
0.6  
0.5  
0.4  
63 125  
42  
31  
-
83  
69  
-
-7  
-13  
DQ  
Slew  
rate  
V/ns  
-
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-
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-11 -14 -13 -13 -18 -27 -29 -45  
-25 -31 -27 -30 -32 -44 -43 -62 -60 -86  
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-45 -53 -50 -67 -61 -85 -78 -109 -108 -152  
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-74 -96 -85 -114 -102 -138 -132 -181 -183 -248  
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-128 -156 -145 -180 -175 -223 -226 -288  
-210 -243 -240 -286 -291 -351  
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value listed in Table x.  
Setup(tDS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VREF(dc) and the first crossing  
of Vih(ac)min. Setup(tDS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VREF(dc) and the  
first crossing of Vil(ac)max. If the actual signal is always earlier than the nominal slew rate line between shaded ‘ VREF(dc) to ac region’,  
use nominal slew rate for derating value(see Fig a.) If the actual signal is later than the nominal slew rate line anywhere between shaded  
‘VREF(dc) to ac region’, the slew rate of a tangent line to the actual signal from the ac level to dc level is used for derating value(see Fig b.)  
Hold(tDH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of Vil(dc) max and the first crossing  
of VREF(dc). Hold (tDH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of Vih(dc) min and the  
first crossing of VREF(dc). If the actual signal is always later than the nominal slew rate line anywhere between shaded ‘dc to VREF(dc)  
region’, the slew rate of a tangent line to the actual signal from the dc level to VREF(dc) level is used for derating value(see Fig c.) If the  
actual signal is earlier than the nominal slew rate line anywhere between shaded ‘dc to VREF(dc) region’, the slew rate of a tangent line  
to the actual signal from the dc level to VREF(dc) level is used for derating value(see Fig d.)  
Although for slow slew rates the total setup time might be negative(i.e. a valid input signal will not have reached VIH/IL(ac) at the time  
of the rising clock transition) a valid input signal is still required to complete the transition and reach VIH/IL(ac).  
For slew rate in between the values listed in table x, the derating valued may obtained by linear interpolation.  
These values are typically not subject to production test. They are verified by design and characterization.  
Rev. 0.4 / Nov 2008  
29  
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