H5PS1G43EFR
H5PS1G83EFR
H5PS1G63EFR
(DDR2-667 and DDR2-800)
DDR2-667
DDR2-800
Symbol
Unit
Note
Parameter
min
max
+450
+400
0.52
min
max
+400
+350
0.52
DQ output access time from CK/CK
DQS output access time from CK/CK
CK HIGH pulse width
tAC
-450
-400
0.48
0.48
-400
-350
0.48
0.48
ps
40
40
tDQSCK
tCH(avg)
tCL(avg)
ps
tCK(avg)
tCK(avg)
35,36
35,36
CK LOW pulse width
0.52
0.52
min(tCL(abs),
tCH(abs))
min(tCL(abs),
tCH(abs))
CK half period
tHP
-
-
ps
37
Clock cycle time, CL=x
tCK(avg)
3000
8000
2500
8000
ps
35,36
DQ and DM input setup time
DQ and DM input hold time
tDS(base)
tDH(base)
100
-
50
-
ps
6,7,8,20,28,31
6,7,8,21,28,31
175
-
125
-
ps
Control & Address input pulse width for each input tIPW
0.6
-
-
0.6
-
-
tCK(avg)
DQ and DM input pulse width for each input
Data-out high-impedance time from CK/CK
DQS low-impedance time from CK/CK
DQ low-impedance time from CK/CK
DQS-DQ skew for DQS and associated DQ signals
DQ hold skew factor
tDIPW
tHZ
0.35
0.35
tCK(avg)
-
tAC max
tAC max
tAC max
240
-
tAC max
tAC max
tAC max
200
ps
ps
ps
ps
ps
ps
18,40
18,40
18,40
13
tLZ(DQS)
tLZ(DQ)
tDQSQ
tQHS
tAC min
tAC min
2*tAC min
2*tAC min
-
-
-
340
-
300
38
DQ/DQS output hold time from DQS
tQH
tHP - tQHS
-
tHP - tQHS
-
39
First DQS latching transition to associated clock
edge
tDQSS
- 0.25
+ 0.25
- 0.25
+ 0.25
tCK(avg)
30
DQS input HIGH pulse width
DQS input LOW pulse width
DQS falling edge to CK setup time
DQS falling edge hold time from CK
Mode register set command cycle time
Write preamble
tDQSH
tDQSL
tDSS
0.35
0.35
0.2
0.2
2
-
0.35
0.35
0.2
0.2
2
-
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
ps
-
-
-
-
30
30
tDSH
-
-
tMRD
-
-
-
-
tWPRE
tWPST
tIS(base)
tIH(base)
tRPRE
tRPST
tRAS
0.35
0.4
200
275
0.9
0.4
45
0.35
0.4
175
250
0.9
0.4
45
Write postamble
0.6
-
0.6
-
10
5,7,9,22,29
5,7,9,23,29
19,41
Address and control input setup time
Address and control input hold time
Read preamble
-
-
ps
1.1
0.6
70000
1.1
0.6
70000
tCK(avg)
tCK(avg)
ns
Read postamble
19,42
Activate to precharge command
3
Active to active command period for 1KB page size
products (x4, x8)
tRRD
tRRD
7.5
10
-
-
7.5
10
-
-
ns
ns
4,32
4,32
Active to active command period for 2KB page size
products (x16)
Four Active Window for 1KB page size products
Four Active Window for 2KB page size products
CAS to CAS command delay
tFAW
tFAW
tCCD
tWR
37.5
-
-
35
-
-
ns
ns
32
32
50
45
2
15
2
15
nCK
ns
Write recovery time
-
-
-
-
32
33
Auto precharge write recovery + precharge time
tDAL
WR+tnRP
WR+tnRP
nCK
Rev. 0.4 / Nov 2008
24
HYNIX [ HYNIX SEMICONDUCTOR ]
