H5PS1G43EFR
H5PS1G83EFR
H5PS1G63EFR
Timing Patterns for 8 bank devices x16
-DDR2-400 all bins: A0 RA0 A1 RA1 A2 RA2 A3 RA3 D D A4 RA4 A5 RA5 A6 RA6 A7 RA7 D D
-DDR2-533 all bins: A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D A4 RA4 D A5 D A6 RA6 D A7 RA7 D D D
-DDR2-667 all bins: A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D A4 RA4 D D A5 RA5 D D A6 RA6 D D A7 RA7
D D D
-DDR2-800 all bins: A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D A4 RA4 D D A5 RA5 D D A6 RA6 D D A7 RA7
D D D D
3.5. Input/Output Capacitance
DDR2 400
DDR2 533
DDR2 667
DDR2 800
Parameter
Symbol
Units
Min
1.0
x
Max
Min
1.0
x
Max
Min
1.0
x
Max
Input capacitance, CK and CK
Input capacitance delta, CK and CK
CCK
CDCK
CI
2.0
0.25
2.0
2.0
0.25
2.0
2.0
0.25
1.75
0.25
3.5
pF
pF
pF
pF
pF
pF
Input capacitance, all other input-only pins
Input capacitance delta, all other input-only pins
Input/output capacitance, DQ, DM, DQS, DQS
Input/output capacitance delta, DQ, DM, DQS, DQS
1.0
x
1.0
x
1.0
x
CDI
0.25
4.0
0.25
3.5
CIO
2.5
x
2.5
x
2.5
x
CDIO
0.5
0.5
0.5
Rev. 0.4 / Nov 2008
20
HYNIX [ HYNIX SEMICONDUCTOR ]
