H5PS1G43EFR
H5PS1G83EFR
H5PS1G63EFR
IDD Testing Parameters
For purposes of IDD testing, the following parameters are to be utilized.
DDR2-800
DDR2-
667
DDR2-
533
DDR2-
400
Parameter
5-5-5
6-6-6
6
5-5-5
5
4-4-4
4
3-3-3
3
Units
CL(IDD)
5
tCK
t
12.5
15
15
15
15
RCD(IDD)
ns
ns
t
57.5
7.5
60
60
60
RC(IDD)
55
t
7.5
ns
ns
RRD(IDD)-x4/x8
7.5
7.5
7.5
t
10
5
RRD(IDD)-x16
10
10
10
3
10
t
2.5
2.5
3.75
CK(IDD)
ns
ns
t
45
70000
12.5
75
45
70000
15
45
70000
15
45
70000
15
40
RASmin(IDD)
t
70000
15
ns
ns
ns
ns
ns
ns
RASmax(IDD)
t
RP(IDD)
t
t
75
75
75
75
RFC(IDD)-256Mb
105
105
105
105
105
127.5
197.5
RFC(IDD)-512Mb
t
t
127.5
197.5
127.5
197.5
127.5
197.5
127.5
197.5
RFC(IDD)-1Gb
RFC(IDD)-2Gb
Detailed IDD7
The detailed timings are shown below for IDD7. Changes will be required if timing parameter changes are made to the
specification.
Legend: A = Active; RA = Read with Autoprecharge; D = Deselect
IDD7: Operating Current: All Bank Interleave Read operation
t
t
All banks are being interleaved at minimum RC(IDD) without violating RRD(IDD) and tFAW (IDD) using a burst length
of 4. Control and address bus inputs are STABLE during DESELECTs. IOUT = 0mA
Timing Patterns for 4 bank devices x4/ x8/ x16
-DDR2-400 4/4/4: A0 RA0 A1 RA1 A2 RA2 A3 RA3 D D D D D
-DDR2-400 3/3/3: A0 RA0 A1 RA1 A2 RA2 A3 RA3 D D D D
-DDR2-533 4/4/4: A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D D D
-DDR2-533 4/4/4: A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D D D
-DDR2-667 5/5/5: A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D D
-DDR2-667 4/4/4: A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D
-DDR2-800 6/6/6: A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D D D D D D
-DDR2-800 5/5/5: A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D D D D D
-DDR2-800 4/4/4: A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D D D D
Timing Patterns for 8 bank devices x4/8
-DDR2-400 all bins: A0 RA0 A1 RA1 A2 RA2 A3 RA3 A4 RA4 A5 RA5 A6 RA6 A7 RA7
-DDR2-533 all bins: A0 RA0 A1 RA1 A2 RA2 A3 RA3 D D A4 RA4 A5 RA5 A6 RA6 A7 RA7 D D
-DDR2-667 all bins: A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D A4 RA4 D A5 RA5 D A6 RA6 D A7 RA7 D D
-DDR2-800 all bins: A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D A4 RA4 D A5 RA5 D A6 RA6 D A7 RA7 D D D
Rev. 0.4 / Nov 2008
19
HYNIX [ HYNIX SEMICONDUCTOR ]
