FT2232C Dual USB UART / FIFO I.C.
Figure 24 - CPU FIFO Dual Channel Interface Example 2
Decoder
FT2232C
CPU
Channel A
15
CS#_A (ACBUS0)
Address Bus
13
12
11
A0_A (ACBUS1)
RD#_A (ACBUS2)
WR#_A (ACBUS3)
RD#
WR#
Data Bus
Data
D[0...7]A (ADBUS[0...7])
Channel B
30
CS#_B (BCBUS0)
A0_B (BCBUS1)
RD#_B (BCBUS2)
WR#B (BCBUS3)
29
28
27
D[0...7]B (BDBUS[0...7])
Figure 24 shows an example where both channels A and B of the FT2232C are used in CPU FIFO mode to interface
with a CPU. This configuration gives the CPU access to both of the FT2232C’s data pipes.
DS2232C Version 1.2
© Future Technology Devices International Ltd. 2004
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