FT2232C Dual USB UART / FIFO I.C.
Status Data bits
Data Bit
Data
1
Status
bit 0
Data Available (=RXF)
bit 1
1
Space Available (=TXE)
bit 2
1
Suspend
bit 3
1
Configured
bit 4 **Note 22
bit 5 **Note 22
bit 6 **Note 22
bit 7 **Note 22
X
X
X
X
X
X
X
X
Key : X = Not Used; 1 = Signal off; 0 = Signal off
**Note 22 : bits 4 to 7 will have arbitrary values when the status is read.
Figure 22 - CPU FIFO Interface Mode - Signal Timing
A0
CS#
WR#
Valid
Valid
t3
t1
t4
t6
RD#
D7..0
Valid
Valid
t2
t5
t7
Time
Description
Min
15
15
20
5
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
t1
t2
t3
t4
t5
t6
t7
t8
t9
A0 / CS Setup to WR#
Data setup to WR#
WR# Pulse width
-
-
-
A0/CS Hold from WR#
Data hold from WR#
A0/CS Setup to RD#
-
5
-
15
15
5
-
Data delay from RD# **Note 23
A0/CS hold from RD#
50
-
Data hold time from RD# **Note 23
0
30
**Note 23 : For standard output drive level Times may vary if high drive level is enabled.
DS2232C Version 1.2
© Future Technology Devices International Ltd. 2004
Page 37 of 54
FTDI [ FUTURE TECHNOLOGY DEVICES INTERNATIONAL LTD. ]
