I2C
2
11.2 I C AC Electrical Specifications
2
Table 40 provides the AC timing parameters for the I C interface of the MPC8540.
2
Table 40. I C AC Electrical Specifications
All values refer to VIH (min) and VIL (max) levels (see Table 39).
Parameter
Symbol 1
Min
Max
Unit
SCL clock frequency
fI2C
0
400
—
kHz
μs
6
Low period of the SCL clock
tI2CL
1.3
0.6
0.6
0.6
6
High period of the SCL clock
tI2CH
—
μs
6
Setup time for a repeated START condition
tI2SVKH
—
μs
6
Hold time (repeated) START condition (after this period, the
first clock pulse is generated)
tI2SXKL
—
μs
6
Data setup time
Data hold time:
tI2DVKH
100
—
ns
tI2DXKL
μs
—
—
CBUS compatible masters
I2C bus devices
0 2
0.9 3
Set-up time for STOP condition
t
0.6
1.3
—
—
—
μs
μs
V
I2PVKH
Bus free time between a STOP and START condition
tI2KHDX
VNL
Noise margin at the LOW level for each connected device
(including hysteresis)
0.1 × OVDD
Noise margin at the HIGH level for each connected device
(including hysteresis)
VNH
0.2 × OVDD
—
V
Notes:
1.The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state)
(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tI2DVKH
symbolizes I2C timing (I2) with respect to the time data input signals (D) reach the valid state (V) relative to the tI2C
clock reference (K) going to the high (H) state or setup time. Also, tI2SXKL symbolizes I2C timing (I2) for the time that
the data with respect to the start condition (S) went invalid (X) relative to the tI2C clock reference (K) going to the low
(L) state or hold time. Also, tI2PVKH symbolizes I2C timing (I2) for the time that the data with respect to the stop
condition (P) reaching the valid state (V) relative to the tI2C clock reference (K) going to the high (H) state or setup
time. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
2.MPC8540 provides a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge
the undefined region of the falling edge of SCL.
3.The maximum tI2DVKH has only to be met if the device does not stretch the LOW period (tI2CL) of the SCL signal.
4.CB = capacitance of one bus line in pF.
6.Guaranteed by design.
2
Figure 17 provides the AC test load for the I C.
OVDD/2
Output
Z0 = 50 Ω
RL = 50 Ω
2
Figure 29. I C AC Test Load
MPC8540 Integrated Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
49
FREESCALE [ Freescale ]
