JTAG
10 JTAG
This section describes the AC electrical specifications for the IEEE 1149.1 (JTAG) interface of the
MPC8540.
Table 38 provides the JTAG AC timing specifications as defined in Figure 25 through Figure 28.
1
Table 38. JTAG AC Timing Specifications (Independent of SYSCLK)
At recommended operating conditions (see Table 2).
Parameter
Symbol 2
Min
Max
Unit
Notes
JTAG external clock frequency of operation
JTAG external clock cycle time
JTAG external clock pulse width measured at 1.4 V
JTAG external clock rise and fall times
TRST assert time
fJTG
t JTG
0
33.3
—
MHz
ns
30
15
0
tJTKHKL
tJTGR & tJTGF
tTRST
—
ns
2
ns
6
3
25
—
ns
Input setup times:
ns
tJTDVKH
tJTIVKH
4
0
—
—
4
4
Boundary-scan data
TMS, TDI
Input hold times:
ns
ns
ns
ns
tJTDXKH
tJTIXKH
20
25
—
—
Boundary-scan data
TMS, TDI
Valid times:
tJTKLDV
tJTKLOV
4
4
20
25
5
Boundary-scan data
TDO
Output hold times:
tJTKLDX
tJTKLOX
5
Boundary-scan data
TDO
JTAG external clock to output high impedance:
tJTKLDZ
tJTKLOZ
3
3
19
9
5, 6
Boundary-scan data
TDO
Notes:
1.All outputs are measured from the midpoint voltage of the falling/rising edge of tTCLK to the midpoint of the signal in
question. The output timings are measured at the pins. All output timings assume a purely resistive 50-Ω load
(see Figure 24). Time-of-flight delays must be added for trace lengths, vias, and connectors in the system.
2.The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state)
(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example,
tJTDVKH symbolizes JTAG device timing (JT) with respect to the time data input signals (D) reaching the valid state
(V) relative to the tJTG clock reference (K) going to the high (H) state or setup time. Also, tJTDXKH symbolizes JTAG
timing (JT) with respect to the time data input signals (D) went invalid (X) relative to the tJTG clock reference (K)
going to the high (H) state. Note that, in general, the clock reference symbol representation is based on three
letters representing the clock of a particular functional. For rise and fall times, the latter convention is used with
the appropriate letter: R (rise) or F (fall).
3.TRST is an asynchronous level sensitive signal. The setup time is for test purposes only.
4.Non-JTAG signal input timing with respect to tTCLK
.
5.Non-JTAG signal output timing with respect to tTCLK
.
6.Guaranteed by design.
MPC8540 Integrated Processor Hardware Specifications, Rev. 4
46
Freescale Semiconductor
FREESCALE [ Freescale ]
