I2C
provides the test access port timing diagram.
JTAG
External Clock
VM
t
JTIVKH
t
JTIXKH
TDI, TMS
t
JTKLOV
t
JTKLOX
TDO
t
JTKLOZ
TDO
Output Data Valid
VM = Midpoint Voltage (OVDD/2)
Output Data Valid
Input
Data Valid
VM
Figure 28. Test Access Port Timing Diagram
11 I
2
C
This section describes the DC and AC electrical characteristics for the I
2
C interface of the MPC8540.
11.1 I
2
C DC Electrical Characteristics
provides the DC electrical characteristics for the I
2
C interface of the MPC8540.
Table 39. I
2
C DC Electrical Characteristics
At recommended operating conditions with OV
DD
of 3.3 V ± 5%.
Parameter
Input high voltage level
Input low voltage level
Low level output voltage
Pulse width of spikes which must be suppressed
by the input filter
Input current each I/O pin (input voltage is
between 0.1
×
OV
DD
and 0.9
×
OV
DD
(max)
Capacitance for each I/O pin
Symbol
V
IH
V
IL
V
OL
t
I2KHKL
I
I
C
I
Min
0.7
×
OV
DD
–0.3
0
0
–10
—
Max
OV
DD
+ 0.3
0.3
×
OV
DD
0.2
×
OV
DD
50
10
10
Unit
V
V
V
ns
μA
pF
Notes
1
2
3
Notes:
1.Output voltage (open drain or open collector) condition = 3 mA sink current.
2.Refer to the
MPC8540 Integrated Processor Preliminary Reference Manual
for information on the digital filter used.
3.I/O pins will obstruct the SDA and SCL lines if OV
DD
is switched off.
MPC8540 Integrated Processor Hardware Specifications, Rev. 4
48
Freescale Semiconductor
FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
