PCI/PCI-X
Table 43. PCI-X AC Timing Specifications at 66 MHz (continued)
Parameter
PCI-X initialization pattern to HRESET setup time
HRESET to PCI-X initialization pattern hold time
Symbol
t
PCIVRH
t
PCRHIX
Min
10
0
Max
—
50
Unit
clocks
ns
Notes
11
6, 11
Notes:
1.See the timing measurement conditions in the
PCI-X 1.0a Specification.
2.Minimum times are measured at the package pin (not the test point). Maximum times are measured with the test point and
load circuit.
3.Setup time for point-to-point signals applies to REQ and GNT only. All other signals are bused.
4.For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered
through the component pin is less than or equal to the leakage current specification.
5.Setup time applies only when the device is not driving the pin. Devices cannot drive and receive signals at the same time.
6.Maximum value is also limited by delay to the first transaction (time for HRESET high to first configuration access, t
PCRHFV
).
The PCI-X initialization pattern control signals after the rising edge of HRESET must be negated no later than two clocks
before the first FRAME and must be floated no later than one clock before FRAME is asserted.
7.A PCI-X device is permitted to have the minimum values shown for t
PCKHOV
and t
CYC
only in PCI-X mode. In conventional
mode, the device must meet the requirements specified in PCI 2.2 for the appropriate clock frequency.
8.Device must meet this specification independent of how many outputs switch simultaneously.
9.The timing parameter t
PCRHFV
is a minimum of 10 clocks rather than the minimum of 5 clocks in the
PCI-X 1.0a Specification.
10.Guaranteed by characterization.
11.Guaranteed by design.
provides the PCI-X AC timing specifications at 133 MHz.
Table 44. PCI-X AC Timing Specifications at 133 MHz
Parameter
SYSCLK to signal valid delay
Output hold from SYSCLK
SYSCLK to output high impedance
Input setup time to SYSCLK
Input hold time from SYSCLK
REQ64 to HRESET setup time
HRESET to REQ64 hold time
HRESET high to first FRAME assertion
PCI-X initialization pattern to HRESET setup time
Symbol
t
PCKHOV
t
PCKHOX
t
PCKHOZ
t
PCIVKH
t
PCIXKH
t
PCRVRH
t
PCRHRX
t
PCRHFV
t
PCIVRH
Min
—
0.7
—
1.4
0.5
10
0
10
10
Max
3.8
—
7
—
—
—
50
—
—
Unit
ns
ns
ns
ns
ns
clocks
ns
clocks
clocks
Notes
1, 2, 3,
7, 8
1, 11
1, 4, 8,
12
3, 5, 9,
11
11
12
12
10, 12
12
MPC8540 Integrated Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
53
FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
