Ethernet: Three-Speed,10/100, MII Management
8.2.2.2
MII Receive AC Timing Specifications
Table 26. MII Receive AC Timing Specifications
provides the MII receive AC timing specifications.
At recommended operating conditions with LV
DD
of 3.3 V ± 5%, or LV
DD
=2.5V ± 5%.
Parameter/Condition
RX_CLK clock period 10 Mbps
RX_CLK clock period 100 Mbps
RX_CLK duty cycle
RXD[3:0], RX_DV, RX_ER setup time to RX_CLK
RXD[3:0], RX_DV, RX_ER hold time to RX_CLK
RX_CLK clock rise and fall time
Symbol
1
t
MRX 3
t
MRX
t
MRXH
/t
MRX
t
MRDVKH
t
MRDXKH
t
MRXR
, t
MRXF 2,3
Min
—
—
35
10.0
10.0
1.0
Typ
400
40
—
—
—
—
Max
—
—
65
—
—
4.0
Unit
ns
ns
%
ns
ns
ns
Note:
1. The symbols used for timing specifications herein follow the pattern of t
(first two letters of functional block)(signal)(state)
(reference)(state)
for inputs and t
(first two letters of functional block)(reference)(state)(signal)(state)
for outputs. For example, t
MRDVKH
symbolizes MII receive timing (MR) with respect to the time data input signals (D) reach the valid state (V) relative to
the t
MRX
clock reference (K) going to the high (H) state or setup time. Also, t
MRDXKL
symbolizes MII receive timing
(GR) with respect to the time data input signals (D) went invalid (X) relative to the t
MRX
clock reference (K) going to
the low (L) state or hold time. Note that, in general, the clock reference symbol representation is based on three letters
representing the clock of a particular functional. For example, the subscript of t
MRX
represents the MII (M) receive
(RX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
2.Signal timings are measured at 0.7 V and 1.9 V voltage levels.
3.Guaranteed by design.
shows the MII receive AC timing diagram.
t
MRX
RX_CLK
t
MRXH
RXD[3:0]
RX_DV
RX_ER
t
MRDVKH
t
MRDXKH
t
MRXF
Valid Data
t
MRXR
Figure 10. MII Receive AC Timing Diagram
MPC8540 Integrated Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
27
FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
