Ethernet: Three-Speed,10/100, MII Management
Table 24. GMII Receive AC Timing Specifications (continued)
At recommended operating conditions with LVDD of 3.3 V 5%, or LVDD=2.5V 5%.
Parameter/Condition
Symbol 1
Min
Typ
Max
Unit
2,3
RX_CLK clock rise and fall time
Note:
1.The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state)
tGRXR, tGRXF
—
—
1.0
ns
(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tGRDVKH
symbolizes GMII receive timing (GR) with respect to the time data input signals (D) reaching the valid state (V) relative
to the tRX clock reference (K) going to the high state (H) or setup time. Also, tGRDXKL symbolizes GMII receive timing
(GR) with respect to the time data input signals (D) went invalid (X) relative to the tGRX clock reference (K) going to
the low (L) state or hold time. Note that, in general, the clock reference symbol representation is based on three letters
representing the clock of a particular functional. For example, the subscript of tGRX represents the GMII (G) receive
(RX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
2.Signal timings are measured at 0.7 V and 1.9 V voltage levels.
3.Guaranteed by design.
Figure 7 provides the AC test load for TSEC.
Output
LVDD/2
Z0 = 50 Ω
RL = 50 Ω
Figure 7. TSEC AC Test Load
Figure 8 shows the GMII receive AC timing diagram.
tGRX
tGRXR
RX_CLK
tGRXF
tGRXH
RXD[7:0]
RX_DV
RX_ER
tGRDXKH
tGRDVKH
Figure 8. GMII Receive AC Timing Diagram
MPC8540 Integrated Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
25
FREESCALE [ Freescale ]
