Ethernet: Three-Speed,10/100, MII Management
8.2.2 MII AC Timing Specifications
This section describes the MII transmit and receive AC timing specifications.
8.2.2.1 MII Transmit AC Timing Specifications
Table 25 provides the MII transmit AC timing specifications.
Table 25. MII Transmit AC Timing Specifications
At recommended operating conditions with LVDD of 3.3 V 5%, or LVDD=2.5V 5%.
Parameter/Condition
TX_CLK clock period 10 Mbps
Symbol 1
Min
Typ
Max
Unit
2
tMTX
—
—
35
1
400
40
—
5
—
—
ns
ns
%
TX_CLK clock period 100 Mbps
TX_CLK duty cycle
tMTX
tMTXH/ MTX
t
65
15
4.0
TX_CLK to MII data TXD[3:0], TX_ER, TX_EN delay
TX_CLK data clock rise and fall time
Note:
tMTKHDX
ns
ns
2,3
tMTXR, tMTXF
1.0
—
1.The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state)
(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMTKHDX
symbolizes MII transmit timing (MT) for the time tMTX clock reference (K) going high (H) until data outputs (D) are
invalid (X). Note that, in general, the clock reference symbol representation is based on two to three letters
representing the clock of a particular functional. For example, the subscript of tMTX represents the MII(M) transmit
(TX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
2.Signal timings are measured at 0.7 V and 1.9 V voltage levels.
3.Guaranteed by design.
Figure 9 shows the MII transmit AC timing diagram.
tMTXR
tMTX
TX_CLK
tMTXF
tMTXH
TXD[3:0]
TX_EN
TX_ER
tMTKHDX
Figure 9. MII Transmit AC Timing Diagram
MPC8540 Integrated Processor Hardware Specifications, Rev. 4
26
Freescale Semiconductor
FREESCALE [ Freescale ]
