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MPC8540CPX667JC 参数 Datasheet PDF下载

MPC8540CPX667JC图片预览
型号: MPC8540CPX667JC
PDF下载: 下载PDF文件 查看货源
内容描述: 集成处理器的硬件规格 [Integrated Processor Hardware Specifications]
分类和应用: 外围集成电路时钟
文件页数/大小: 104 页 / 1354 K
品牌: FREESCALE [ Freescale ]
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Ethernet: Three-Speed,10/100, MII Management  
Table 23. GMII Transmit AC Timing Specifications (continued)  
At recommended operating conditions with LVDD of 3.3 V 5%, or LVDD=2.5V 5%.  
Parameter/Condition  
Symbol 1  
Min  
Typ  
Max  
Unit  
2,4  
GTX_CLK data clock rise and fall time  
tGTXR, tGTXF  
1.0  
ns  
Notes:  
1. The symbols used for timing specifications herein follow the pattern t(first two letters of functional block)(signal)(state)  
(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tGTKHDV  
symbolizes GMII transmit timing (GT) with respect to the tGTX clock reference (K) going to the high state (H) relative  
to the time date input signals (D) reaching the valid state (V) to state or setup time. Also, tGTKHDX symbolizes GMII  
transmit timing (GT) with respect to the tGTX clock reference (K) going to the high state (H) relative to the time date  
input signals (D) going invalid (X) or hold time. Note that, in general, the clock reference symbol representation is  
based on three letters representing the clock of a particular functional. For example, the subscript of tGTX represents  
the GMII(G) transmit (TX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R  
(rise) or F (fall).  
2.Signal timings are measured at 0.7 V and 1.9 V voltage levels.  
3.Guaranteed by characterization.  
4.Guaranteed by design.  
Figure 6 shows the GMII transmit AC timing diagram.  
tGTX  
tGTXR  
GTX_CLK  
tGTXF  
tGTXH  
TXD[7:0]  
TX_EN  
TX_ER  
tGTKHDX  
tGTKHDV  
Figure 6. GMII Transmit AC Timing Diagram  
8.2.1.2 GMII Receive AC Timing Specifications  
Table 24 provides the GMII receive AC timing specifications.  
Table 24. GMII Receive AC Timing Specifications  
At recommended operating conditions with LVDD of 3.3 V 5%, or LVDD=2.5V 5%.  
Parameter/Condition  
RX_CLK clock period  
Symbol 1  
Min  
Typ  
Max  
Unit  
tGRX  
40  
8.0  
60  
ns  
ns  
ns  
ns  
RX_CLK duty cycle  
tGRXH/tGRX  
tGRDVKH  
tGRDXKH  
RXD[7:0], RX_DV, RX_ER setup time to RX_CLK  
RXD[7:0], RX_DV, RX_ER hold time to RX_CLK  
2.0  
0.5  
MPC8540 Integrated Processor Hardware Specifications, Rev. 4  
24  
Freescale Semiconductor  
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