Ethernet: Three-Speed,10/100, MII Management
8.2.3 TBI AC Timing Specifications
This section describes the TBI transmit and receive AC timing specifications.
8.2.3.1 TBI Transmit AC Timing Specifications
Table 27 provides the TBI transmit AC timing specifications.
Table 27. TBI Transmit AC Timing Specifications
At recommended operating conditions with LVDD of 3.3 V 5%, or LVDD=2.5V 5%.
Parameter/Condition
GTX_CLK clock period
Symbol 1
Min
Typ
Max
Unit
tTTX
—
40
2.0
1.0
—
8.0
—
—
—
—
—
60
—
ns
%
GTX_CLK duty cycle
tTTXH/tTTX
tTTKHDV
tTTKHDX
TCG[9:0] setup time GTX_CLK going high
TCG[9:0] hold time from GTX_CLK going high
GTX_CLK clock rise and fall time
Notes:
ns
ns
ns
—
2,3
tTTXR, tTTXF
1.0
1.The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state
)(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tTTKHDV
symbolizes the TBI transmit timing (TT) with respect to the time from tTTX (K) going high (H) until the referenced data
signals (D) reach the valid state (V) or setup time. Also, tTTKHDX symbolizes the TBI transmit timing (TT) with respect
to the time from tTTX (K) going high (H) until the referenced data signals (D) reach the invalid state (X) or hold time.
Note that, in general, the clock reference symbol representation is based on three letters representing the clock of a
particular functional. For example, the subscript of tTTX represents the TBI (T) transmit (TX) clock. For rise and fall
times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
2.Signal timings are measured at 0.7 V and 1.9 V voltage levels.
3.Guaranteed by design.
Figure 11 shows the TBI transmit AC timing diagram.
tTTXR
tTTX
GTX_CLK
TCG[9:0]
tTTXH
tTTXF
tTTKHDV
tTTKHDX
Figure 11. TBI Transmit AC Timing Diagram
MPC8540 Integrated Processor Hardware Specifications, Rev. 4
28
Freescale Semiconductor
FREESCALE [ Freescale ]
