Ethernet: Three-Speed,10/100, MII Management
8 Ethernet: Three-Speed,10/100, MII Management
This section provides the AC and DC electrical characteristics for three-speed, 10/100, and MII
management.
8.1 Three-Speed Ethernet Controller (TSEC)
(10/100/1Gb Mbps)—GMII/MII/TBI/RGMII/RTBI Electrical
Characteristics
The electrical characteristics specified here apply to all GMII (gigabit media independent interface), MII
(media independent interface), TBI (ten-bit interface), RGMII (reduced gigabit media independent
interface), and RTBI (reduced ten-bit interface) signals except MDIO (management data input/output) and
MDC (management data clock). The RGMII and RTBI interfaces are defined for 2.5 V, while the GMII,
MII, and TBI interfaces can be operated at 3.3 or 2.5 V. Whether the GMII, MII, or TBI interface is
operated at 3.3 or 2.5 V, the timing is compliant with the IEEE 802.3 standard. The RGMII and RTBI
interfaces follow the Hewlett-Packard reduced pin-count interface for Gigabit Ethernet Physical Layer
Device Specification Version 1.2a (9/22/2000). The electrical characteristics for MDIO and MDC are
specified in
8.1.1 TSEC DC Electrical Characteristics
All GMII, MII, TBI, RGMII, and RTBI drivers and receivers comply with the DC parametric attributes
specified in
and
The potential applied to the input of a GMII, MII, TBI, RGMII, or
RTBI receiver may exceed the potential of the receiver’s power supply (i.e., a GMII driver powered from
a 3.6 V supply driving V
OH
into a GMII receiver powered from a 2.5 V supply). Tolerance for dissimilar
GMII driver and receiver supply potentials is implicit in these specifications. The RGMII and RTBI signals
are based on a 2.5 V CMOS interface voltage as defined by JEDEC EIA/JESD8-5.
Table 21. GMII, MII, and TBI DC Electrical Characteristics
Parameter
Supply voltage 3.3 V
Output high voltage
(LV
DD
= Min, I
OH
= –4.0 mA)
Output low voltage
(LV
DD
= Min, I
OL
= 4.0 mA)
Input high voltage
Input low voltage
Input high current
(V
IN 1
= LV
DD
)
Input low current
(V
IN 1
= GND)
Symbol
LV
DD
V
OH
V
OL
V
IH
V
IL
I
IH
I
IL
Min
3.13
2.40
Max
3.47
LV
DD
+ 0.3
0.50
Unit
V
V
GND
V
1.70
–0.3
—
LV
DD
+ 0.3
0.90
40
V
V
μA
μA
–600
—
Note:
1.The symbol V
IN
, in this case, represents the LV
IN
symbol referenced in
and
MPC8540 Integrated Processor Hardware Specifications, Rev. 4
22
Freescale Semiconductor