Port Integration Module (S12PPIMV1)
Table 2-3. Pin Configuration Summary
DDR
IO
RDR
PE
PS(1)
IE(2)
Function
Pull Device
Interrupt
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
x
x
x
x
x
x
x
0
1
0
1
0
1
0
1
x
x
x
x
x
x
x
0
0
1
1
0
0
1
1
0
1
1
0
0
1
1
x
x
x
x
x
x
x
x
x
0
1
0
1
0
1
x
x
x
x
0
1
0
1
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Input
Input
Input
Input
Input
Input
Input
Disabled
Pull Up
Disabled
Disabled
Pull Down
Disabled
Disabled
Pull Up
Disabled
Falling edge
Rising edge
Falling edge
Rising edge
Disabled
Pull Down
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Output, full drive to 0
Output, full drive to 1
Disabled
Output, reduced drive to 0
Output, reduced drive to 1
Output, full drive to 0
Disabled
Disabled
Falling edge
Rising edge
Falling edge
Rising edge
Output, full drive to 1
Output, reduced drive to 0
Output, reduced drive to 1
1. Always “0” on Port A, B, E, and AD.
2. Applicable only on Port P and J.
NOTE
All register bits in this module are completely synchronous to internal
clocks during a register read.
NOTE
Figure of port data registers also display the alternative functions if
applicable on the related pin as defined in Table 2-1. Names in brackets
denote the availability of the function when using a specific routing option.
NOTE
Figures of module routing registers also display the module instance or
module channel associated with the related routing bit.
S12P-Family Reference Manual, Rev. 1.13
62
Freescale Semiconductor
FREESCALE [ Freescale ]
