Port Integration Module (S12PPIMV1)
2.3.7
PIM Reserved Register
Address 0x0004 to 0x0007
Access: User read(1)
7
6
5
4
3
2
1
0
R
W
0
0
0
0
0
0
0
0
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 2-5. PIM Reserved Register
1. Read: Always reads 0x00
Write: Unimplemented
2.3.8
Port E Data Register (PORTE)
Address 0x0008
Access: User read/write(1)
7
6
5
4
3
2
1
0
R
PE1
PE0
PE7
PE6
PE5
PE4
PE3
PE2
W
Altern.
Function
ECLKX2
0
—
0
—
0
ECLK
0
—
0
—
0
IRQ
XIRQ
(2)
2
Reset
—
—
= Unimplemented or Reserved
Figure 2-6. Port E Data Register (PORTE)
1. Read: Anytime. The data source is depending on the data direction value.
Write: Anytime
2. These registers are reset to zero. Two bus clock cycles after reset release the register values are updated with the associated
pin values.
Table 2-8. PORTE Register Field Descriptions
Field
Description
7
PE
Port E general purpose input/output data—Data Register, ECLKX2 output
When not used with the alternative function, the associated pin can be used as general purpose I/O. In general
purpose output mode the register bit value is driven to the pin.
If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered
pin input state is read.
• The ECLKX2 output function takes precedence over the general purpose I/O function if enabled.
6-5, 3-2 Port E general purpose input/output data—Data Register
PE
The associated pin can be used as general purpose I/O. In general purpose output mode the register bit value is
driven to the pin.
If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered
pin input state is read.
S12P-Family Reference Manual, Rev. 1.13
Freescale Semiconductor
65
FREESCALE [ Freescale ]
