Port Integration Module (S12PPIMV1)
Register
Bit 7
6
5
4
3
WOMS3
0
2
WOMS2
0
1
WOMS1
0
Bit 0
WOMS0
0
Name
0x024E
WOMS
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
0x024F
Reserved
R
0
0
0
0
0
0
0
0
0
0
0
W
0x0250
PTM
R
PTM5
PTM4
PTM3
PTM2
PTM1
PTM0
W
0x0251
PTIM
R
PTIM5
PTIM4
PTIM3
PTIM2
PTIM1
PTIM0
W
0x0252
DDRM
R
DDRM5
RDRM5
PERM5
PPSM5
DDRM4
RDRM4
PERM4
PPSM4
DDRM3
RDRM3
PERM3
PPSM3
DDRM2
RDRM2
PERM2
PPSM2
DDRM1
RDRM1
PERM1
PPSM1
DDRM0
RDRM0
PERM0
PPSM0
W
0x0253
RDRM
R
W
0x0254
PERM
R
W
0x0255
PPSM
R
W
0x0256
WOMM
R
WOMM5
0
WOMM4
0
WOMM3
0
WOMM2
0
WOMM1
0
WOMM0
0
W
0x0257
Reserved
R
W
0x0258
PTP
R
PTP7
PTP5
PTP4
PTP3
PTP2
PTP1
PTP0
W
0x0259
PTIP
R
PTIP7
PTIP5
PTIP4
PTIP3
PTIP2
PTIP1
PTIP0
W
0x025A
DDRP
R
DDRP7
RDRP7
PERP7
PPSP7
DDRP5
RDRP5
PERP5
PPSP5
DDRP4
RDRP4
PERP4
PPSP4
DDRP3
RDRP3
PERP3
PPSP3
DDRP2
RDRP2
PERP2
PPSP2
DDRP1
RDRP1
PERP1
PPSP1
DDRP0
RDRP0
PERP0
PPSP0
W
0x025B
RDRP
R
W
0x025C
PERP
R
W
0x025D
PPSP
R
W
= Unimplemented or Reserved
S12P-Family Reference Manual, Rev. 1.13
58
Freescale Semiconductor