Port Integration Module (S12PPIMV1)
2.3.5
Port A Data Direction Register (DDRA)
Address 0x0002
Access: User read/write(1)
7
6
5
4
3
2
1
0
R
DDRA7
DDRA6
DDRA5
DDRA4
DDRA3
DDRA2
DDRA1
DDRA0
W
Reset
0
0
0
0
0
0
0
0
Figure 2-3. Port A Data Direction Register (DDRA)
1. Read: Anytime
Write: Anytime
Table 2-6. DDRA Register Field Descriptions
Description
Field
7-0
Port A Data Direction—
DDRA
This bit determines whether the associated pin is an input or output.
1 Associated pin is configured as output
0 Associated pin is configured as input
2.3.6
Port B Data Direction Register (DDRB)
Address 0x0003
Access: User read/write(1)
7
6
5
4
3
2
1
0
R
DDRB7
DDRB6
DDRB5
DDRB4
DDRB3
DDRB2
DDRB1
DDRB0
W
Reset
0
0
0
0
0
0
0
0
Figure 2-4. Port B Data Direction Register (DDRB)
1. Read: Anytime
Write: Anytime
Table 2-7. DDRB Register Field Descriptions
Description
Field
7-0
Port B Data Direction—
DDRB
This bit determines whether the associated pin is an input or output.
1 Associated pin is configured as output
0 Associated pin is configured as input
S12P-Family Reference Manual, Rev. 1.13
64
Freescale Semiconductor
FREESCALE [ Freescale ]
