Port Integration Module (S12PPIMV1)
Table 2-8. PORTE Register Field Descriptions (continued)
Field
Description
4
PE
Port E general purpose input/output data—Data Register, ECLK output
When not used with the alternative function, the associated pin can be used as general purpose I/O. In general
purpose output mode the register bit value is driven to the pin.
If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered
pin input state is read.
• The ECLK output function takes precedence over the general purpose I/O function if enabled.
1
Port E general purpose input data and interrupt—Data Register, IRQ input.
PE
This pin can be used as general purpose and IRQ input.
0
Port E general purpose input data and interrupt—Data Register, XIRQ input.
PE
This pin can be used as general purpose and XIRQ input.
2.3.9
Port E Data Direction Register (DDRE)
Address 0x0009
Access: User read/write(1)
7
6
5
4
3
2
1
0
R
0
0
DDRE7
DDRE6
DDRE5
DDRE4
DDRE3
DDRE2
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 2-7. Port E Data Direction Register (DDRE)
1. Read: Anytime
Write: Anytime
Table 2-9. DDRE Register Field Descriptions
Description
Field
7-2
Port E Data Direction—
DDRE
This bit determines whether the associated pin is an input or output.
1 Associated pin is configured as output
0 Associated pin is configured as input
S12P-Family Reference Manual, Rev. 1.13
66
Freescale Semiconductor
FREESCALE [ Freescale ]
