Timer Interface A (TIMA)
I/O Registers
16.7.2 TIMA Counter Registers
The two read-only TIMA counter registers contain the high and low bytes of the
value in the TIMA counter. Reading the high byte (TACNTH) latches the contents
of the low byte (TACNTL) into a buffer. Subsequent reads of TACNTH do not affect
the latched TACNTL value until TACNTL is read. Reset clears the TIMA counter
registers. Setting the TIMA reset bit (TRST) also clears the TIMA counter registers.
NOTE:
If TACNTH is read during a break interrupt, be sure to unlatch TACNTL by reading
TACNTL before exiting the break interrupt. Otherwise, TACNTL retains the value
latched during the break.
Register Name and Address:
Bit 7
TACNTH — $000F
6
Bit 14
R
5
Bit 13
R
4
3
Bit 11
R
2
Bit 10
R
1
Bit 9
R
Bit 0
Bit 8
R
Read:
Write:
Reset:
Bit 15
Bit 12
R
0
R
0
0
0
0
0
0
0
Register Name and Address:
Bit 7
TACNTL — $0010
6
5
Bit 5
R
4
3
Bit 3
R
2
Bit 2
R
1
Bit 1
R
Bit 0
Bit 0
R
Read:
Write:
Reset:
Bit 7
R
Bit 6
Bit 4
R
R
0
0
0
0
0
0
0
0
R
= Reserved
Figure 16-6. TIMA Counter Registers (TACNTH and TACNTL)
MC68HC908MR32 • MC68HC908MR16 — Rev. 6.0
MOTOROLA
Data Sheet
247
Timer Interface A (TIMA)
FREESCALE [ Freescale ]
