Timer Interface A (TIMA)
16.4 Interrupts
These TIMA sources can generate interrupt requests:
•
TIMA overflow flag (TOF) — The timer overflow flag (TOF) bit is set when
the TIMA counter reaches the modulo value programmed in the TIMA
counter modulo registers. The TIMA overflow interrupt enable bit, TOIE,
enables TIMA overflow interrupt requests. TOF and TOIE are in the TIMA
status and control registers.
•
TIMA channel flags (CH3F–CH0F) — The CHxF bit is set when an input
capture or output compare occurs on channel x. Channel x TIMA CPU
interrupt requests are controlled by the channel x interrupt enable bit,
CHxIE.
16.5 Wait Mode
The WAIT instruction puts the MCU in low power-consumption standby mode.
The TIMA remains active after the execution of a WAIT instruction. In wait mode,
the TIMA registers are not accessible by the CPU. Any enabled CPU interrupt
request from the TIMA can bring the MCU out of wait mode.
If TIMA functions are not required during wait mode, reduce power consumption by
stopping the TIMA before executing the WAIT instruction.
16.6 I/O Signals
Port E shares five of its pins with the TIMA:
•
•
PTE3/TCLKA is an external clock input to the TIMA prescaler.
The four TIMA channel I/O pins are PTE4/TCH0A, PTE5/TCH1A,
PTE6/TCH2A, and PTE7/TCH3A.
16.6.1 TIMA Clock Pin (PTE3/TCLKA)
PTE3/TCLKA is an external clock input that can be the clock source for the TIMA
counter instead of the prescaled internal bus clock. Select the PTE3/TCLKA input
by writing logic 1s to the three prescaler select bits, PS[2:0]. See 16.7.1 TIMA
Status and Control Register.
The maximum TCLK frequency is the least: 4 MHz or bus frequency ÷ 2.
PTE3/TCLKA is available as a general-purpose I/O pin when not used as the TIMA
clock input. When the PTE3/TCLKA pin is the TIMA clock input, it is an input
regardless of the state of the DDRE3 bit in data direction register E.
Data Sheet
244
MC68HC908MR32 • MC68HC908MR16 — Rev. 6.0
Timer Interface A (TIMA)
MOTOROLA
FREESCALE [ Freescale ]
