Timer Interface A (TIMA)
cannot be lost due to inadvertent clearing of TOF. Reset clears the TOF bit.
Writing a logic 1 to TOF has no effect.
1 = TIMA counter has reached modulo value.
0 = TIMA counter has not reached modulo value.
TOIE — TIMA Overflow Interrupt Enable Bit
This read/write bit enables TIMA overflow interrupts when the TOF bit becomes
set. Reset clears the TOIE bit.
1 = TIMA overflow interrupts enabled
0 = TIMA overflow interrupts disabled
TSTOP — TIMA Stop Bit
This read/write bit stops the TIMA counter. Counting resumes when TSTOP is
cleared. Reset sets the TSTOP bit, stopping the TIMA counter until software
clears the TSTOP bit.
1 = TIMA counter stopped
0 = TIMA counter active
NOTE:
Do not set the TSTOP bit before entering wait mode if the TIMA is required to exit
wait mode. Also when the TSTOP bit is set and the timer is configured for input
capture operation, input captures are inhibited until the TSTOP bit is cleared.
TRST — TIMA Reset Bit
Setting this write-only bit resets the TIMA counter and the TIMA prescaler.
Setting TRST has no effect on any other registers. Counting resumes from
$0000. TRST is cleared automatically after the TIMA counter is reset and
always reads as logic 0. Reset clears the TRST bit.
1 = Prescaler and TIMA counter cleared
0 = No effect
NOTE:
Setting the TSTOP and TRST bits simultaneously stops the TIMA counter at a
value of $0000.
PS[2:0] — Prescaler Select Bits
These read/write bits select either the PTE3/TCLKA pin or one of the seven
prescaler outputs as the input to the TIMA counter as Table 16-1 shows. Reset
clears the PS[2:0] bits.
Table 16-1. Prescaler Selection
PS[2:0]
000
TIMA Clock Source
Internal bus clock ÷1
Internal bus clock ÷ 2
Internal bus clock ÷ 4
Internal bus clock ÷ 8
Internal bus clock ÷ 16
Internal bus clock ÷ 32
Internal bus clock ÷ 64
PTE3/TCLKA
001
010
011
100
101
110
111
Data Sheet
246
MC68HC908MR32 • MC68HC908MR16 — Rev. 6.0
MOTOROLA
Timer Interface A (TIMA)
FREESCALE [ Freescale ]
