Freescale Semiconductor, Inc.
Memory Map
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
$0034
Read:
Timer A Channel 4 Register
Bit 7
6
5
4
3
2
1
Bit 0
Low (TACH4L) Write:
See page 403.
Reset:
Indeterminate after reset
$0035
$0036
$0037
$0038
$0039
$003A
$003B
$003C
$003D
Read: CH5F
0
R
0
Timer A Channel 5 Status and
CH5IE
0
MS5A
0
ELS5B ELS5A
TOV5 CH5MAX
Control Register (TASC5) Write:
0
0
See page 397.
Reset:
0
0
0
9
0
Read:
Timer A Channel 5 Register
Bit 15
14
13
12
11
10
Bit 8
High (TACH5H) Write:
See page 403.
Reset:
Indeterminate after reset
Read:
Timer A Channel 5 Register
Bit 7
6
5
4
3
2
1
Bit 0
Low (TACH5L) Write:
See page 403.
Reset:
Indeterminate after reset
ADCH4 ADCH3 ADCH2 ADCH1 ADCH0
Read: COCO
Analog-to-Digital Status and
AIEN
ADCO
Control Register (ADSCR) Write:
R
0
See page 413.
Reset:
0
AD6
R
0
AD5
R
1
AD4
R
1
AD3
R
1
AD2
R
1
AD1
R
1
AD0
R
Read: AD7
Analog-to-Digital Data Register
See page 416.
(ADR) Write:
R
Indeterminate after reset
Reset:
Read:
0
0
R
0
0
R
0
0
R
0
Analog-to-Digital Input Clock
ADIV2
0
ADIV1
ADIV0 ADICLK
Register (ADICLK) Write:
R
0
See page 416.
Reset:
0
RXPOL
1
0
0
0
0
Read:
BDLC Analog and Roundtrip
ATE
1
BO3
BO2
BO1
1
BO0
1
Delay Register (BARD) Write:
See page 358.
Reset:
0
R1
1
0
R0
0
0
1
0
Read:
BDLC Control Register 1
IMSG
1
CLKS
1
IE
0
WCM
0
(BCR1) Write:
R
0
R
0
See page 359.
Reset:
0
Read:
BDLC Control Register 2
ALOOP DLOOP RX4XE
NBFS
TEOD
TSIFR TMIFR1 TMIFR0
(BCR2) Write:
See page 362.
Reset:
1
1
0
0
0
0
0
0
= Unimplemented
R
= Reserved
U = Unaffected
Figure 2-2. Control, Status, and Data Registers (Sheet 6 of 9)
Technical Data
MC68HC908AS60 — Rev. 1.0
Memory Map
For More Information On This Product,
Go to: www.freescale.com
FREESCALE [ Freescale ]
