Freescale Semiconductor, Inc.
Memory Map
Addr.
Register Name
Bit 7
LVISTOP
0
6
R
5
4
3
2
1
STOP
0
Bit 0
COPD
0
$001F
Read:
Configuration Write-Once
LVIRST LVIPWR SSREC COPL
Register (CONFIG-1) Write:
See page 182.
Reset:
1
1
TSTOP
1
1
0
0
0
0
PS2
0
$0020
Read: TOF
Timer A Status and Control
TOIE
0
PS1
0
PS0
0
Register (TASC) Write:
See page 393.
0
0
TRST
0
R
0
Reset:
$0021
$0022
Unimplemented
Read: Bit 15
14
R
0
13
R
0
12
R
0
11
R
0
10
R
0
9
R
0
Bit 8
R
Timer A Counter Register
See page 395.
High (TACNTH) Write:
R
0
Reset:
0
$0023
$0024
$0025
$0026
$0027
$0028
$0029
Read: Bit 7
6
5
4
3
2
1
Bit 0
R
Timer A Counter Register
See page 395.
Low (TACNTL) Write:
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Reset:
Read:
0
Timer A Modulo Register
Bit 15
1
14
13
12
11
1
10
1
9
1
1
1
Bit 8
1
High (TAMODH) Write:
See page 396.
Reset:
1
1
1
Read:
Timer A Modulo Register
Bit 7
1
6
1
5
1
4
1
3
2
Bit 0
1
Low (TAMODL) Write:
See page 396.
Reset:
1
1
Read: CH0F
Timer A Channel 0 Status and
CH0IE
0
MS0B
0
MS0A
0
ELS0B ELS0A
TOV0 CH0MAX
Control Register (TASC0) Write:
0
0
See page 397.
Reset:
0
0
0
9
0
Read:
Timer A Channel 0 Register
Bit 15
14
13
12
11
10
Bit 8
High (TACH0H) Write:
See page 403.
Reset:
Indeterminate after reset
Read:
Timer A Channel 0 Register
Bit 7
6
5
4
3
2
1
Bit 0
Low (TACH0L) Write:
See page 403.
Reset:
Indeterminate after reset
Read: CH1F
0
R
0
Timer A Channel 1 Status and
CH1IE
0
MS1A
ELS1B ELS1A
TOV1 CH1MAX
Control Register (TASC1) Write:
0
0
See page 397.
Reset:
0
0
0
0
0
= Unimplemented
R
= Reserved
U = Unaffected
Figure 2-2. Control, Status, and Data Registers (Sheet 4 of 9)
Technical Data
MC68HC908AS60 — Rev. 1.0
Memory Map
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