Freescale Semiconductor, Inc.
Memory Map
Addr.
Register Name
Bit 7
0
6
0
5
0
4
0
3
0
2
1
Bit 0
$000A
Read:
Port G Data Register
PTG2
PTG1
PTG0
(PTG) Write:
R
R
R
R
R
See page 320.
Reset:
Read:
Unaffected by reset
$000B
$000C
$000D
$000E
$000F
$0010
$0011
0
0
0
0
0
0
Port H Data Register
PTH1
PTH0
(PTH) Write:
R
R
R
R
R
R
See page 323.
Reset:
Read:
Unaffected by reset
DDRE7 DDRE6 DDRE5 DDRE4 DDRE3 DDRE2 DDRE1 DDRE0
Data Direction Register E
(DDRE) Write:
See page 316.
Reset:
Read:
0
0
0
0
0
0
0
0
0
Data Direction Register F
DDRF6 DDRF5 DDRF4 DDRF3 DDRF2 DDRF1 DDRF0
(DDRF) Write:
R
0
See page 319.
Reset:
Read:
0
0
0
0
0
0
0
0
0
0
0
0
Data Direction Register G
DDRG2 DDRG1 DDRG0
(DDRG) Write:
R
0
R
0
R
0
R
0
R
0
See page 321.
Reset:
Read:
0
0
0
0
0
0
0
0
0
Data Direction Register H
DDRH1 DDRH0
(DDRH) Write:
R
0
R
0
R
0
R
0
R
0
R
0
See page 324.
Reset:
Read:
0
0
SPI Control Register
SPRIE
R
0
SPMSTR CPOL
CPHA SPWOM SPE
SPTIE
0
(SPCR) Write:
See page 283.
Reset:
0
1
OVRF
R
0
MODF
R
1
SPTE
R
0
0
Read: SPRF
SPI Status and Control
ERRIE
MODFEN SPR1
SPR0
Register (SPSCR) Write:
R
0
See page 286.
Reset:
0
0
0
1
0
0
0
$0012
$0013
Read:
R7
T7
R6
T6
R5
T5
R4
R3
T3
R2
T2
R1
T1
R0
T0
SPI Data Register
(SPDR) Write:
T4
See page 289.
Reset:
Indeterminate after reset
Read:
SCI Control Register 1
LOOPS ENSCI TXINV
M
WAKE
ILTY
0
PEN
0
PTY
0
(SCC1) Write:
See page 243.
Reset:
0
0
0
0
0
= Unimplemented
R
= Reserved
U = Unaffected
Figure 2-2. Control, Status, and Data Registers (Sheet 2 of 9)
Technical Data
MC68HC908AS60 — Rev. 1.0
Memory Map
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