Freescale Semiconductor, Inc.
Memory Map
Input/Output Section
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
$003E
Read:
0
0
I3
I2
I1
I0
0
0
BDLC State Vector Register
(BSVR) Write:
See page 370.
Reset:
Read:
0
0
0
0
0
0
0
0
$003F
BDLC Data Register
BD7
BD6
BD5
BD4
BD3
BD2
BD1
BD0
(BDR) Write:
See page 372.
Reset:
Indeterminate after reset
$0040
↓
$004A
Unimplemented
$004B
$004C
$004D
$004E
$004F
$FE00
Read: TOF
0
TRST
0
0
TIM Status and Control
See page 296.
TOIE
TSTOP
PS2
PS1
PS0
Register (TSC) Write:
0
0
Reset:
0
1
0
0
0
9
0
Read: Bit 15
14
13
12
11
10
Bit 8
TIM Counter Register High
(TCNTH) Write:
See page 298.
Reset:
0
0
6
0
5
0
4
0
3
0
2
0
1
0
Read: Bit 7
Bit 0
TIM Counter Register Low
(TCNTL) Write:
See page 298.
Reset:
Read:
0
Bit 15
1
0
14
1
0
13
1
0
12
1
0
11
1
0
10
1
0
9
1
1
0
Bit 8
1
TIM Modulo Register High
(TMODH) Write:
See page 299.
Reset:
Read:
TIM Modulo Register Low
Bit 7
1
6
5
4
3
2
Bit 0
1
(TMODL) Write:
See page 299.
Reset:
Read:
1
1
1
1
1
1
SBSW
See Note
0
SIM Break Status Register
R
R
R
R
R
R
R
(SBSR) Write:
See page 151.
Reset:
Note: Writing a logic 0 clears SBSW.
$FE01
Read: POR
PIN
COP
ILOP
ILAD
0
0
LVI
0
0
0
SIM Reset Status Register
(SRSR) Write:
See page 153.
Reset:
1
0
0
0
0
= Unimplemented
R
= Reserved
U = Unaffected
Figure 2-2. Control, Status, and Data Registers (Sheet 7 of 9)
MC68HC908AS60 — Rev. 1.0
Technical Data
Memory Map
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