Freescale Semiconductor, Inc.
Memory Map
Input/Output Section
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
$002A
Read:
Timer A Channel 1 Register
Bit 15
14
13
12
11
10
9
Bit 8
High (TACH1H) Write:
See page 403.
Reset:
Indeterminate after reset
$002B
$002C
$002D
$002E
$002F
$0030
$0031
$0032
$0033
Read:
Timer A Channel 1 Register
Bit 7
6
5
4
3
2
1
Bit 0
Low (TACH1L) Write:
See page 403.
Reset:
Indeterminate after reset
Read: CH2F
Timer A Channel 2 Status and
CH2IE
0
MS2B
0
MS2A
0
ELS2B ELS2A
TOV2 CH2MAX
Control Register (TASC2) Write:
0
0
See page 397.
Reset:
0
0
0
9
0
Read:
Timer A Channel 2 Register
Bit 15
14
13
12
11
10
Bit 8
High (TACH2H) Write:
See page 403.
Reset:
Indeterminate after reset
Read:
Timer A Channel 2 Register
Bit 7
6
5
4
3
2
1
Bit 0
Low (TACH2L) Write:
See page 403.
Reset:
Indeterminate after reset
Read: CH3F
0
R
0
Timer A Channel 3 Status and
CH3IE
0
MS3A
0
ELS3B ELS3A
TOV3 CH3MAX
Control Register (TASC3) Write:
0
0
See page 397.
Reset:
0
0
0
9
0
Read:
Timer A Channel 3 Register
Bit 15
14
13
12
11
10
Bit 8
High (TACH3H) Write:
See page 403.
Reset:
Indeterminate after reset
Read:
Timer A Channel 3 Register
Bit 7
6
5
4
3
2
1
Bit 0
Low (TACH3L) Write:
See page 403.
Reset:
Indeterminate after reset
Read: CH4F
Timer A Channel 4 Status and
CH4IE
0
MS4B
0
MS4A
0
ELS4B ELS4A
TOV4 CH4MAX
Control Register (TASC4) Write:
0
0
See page 397.
Reset:
0
0
0
9
0
Read:
Timer A Channel 4 Register
Bit 15
14
13
12
11
10
Bit 8
High (TACH4H) Write:
See page 403.
Reset:
Indeterminate after reset
= Reserved
= Unimplemented
R
U = Unaffected
Figure 2-2. Control, Status, and Data Registers (Sheet 5 of 9)
MC68HC908AS60 — Rev. 1.0
Technical Data
Memory Map
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