Freescale Semiconductor, Inc.
Memory Map
Input/Output Section
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Port A Data Register
PTA7
PTA6
PTA5
PTA4
PTA3
PTA2
PTA1
PTA0
$0000
(PTA) Write:
See page 304.
Reset:
Read:
Unaffected by reset
PTB4 PTB3
Unaffected by reset
PTC4 PTC3
Unaffected by reset
PTD4 PTD3
Unaffected by reset
Port B Data Register
PTB7
PTB6
PTB5
PTC5
PTD5
PTB2
PTC2
PTD2
PTB1
PTC1
PTD1
PTB0
PTC0
PTD0
$0001
$0002
$0003
$0004
$0005
$0006
$0007
$0008
$0009
(PTB) Write:
See page 306.
Reset:
Read:
0
0
Port C Data Register
(PTC) Write:
See page 308.
R
R
Reset:
Read:
Port D Data Register
PTD7
PTD6
(PTD) Write:
See page 311.
Reset:
Read:
Data Direction Register A
DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0
Unaffected by reset
(DDRA) Write:
See page 304.
Reset:
Read:
Data Direction Register B
DDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0
(DDRB) Write:
See page 307.
Reset:
Read:
0
MCLKEN
0
0
0
0
0
0
0
0
0
Data Direction Register C
DDRC5 DDRC4 DDRC3 DDRC2 DDRC1 DDRC0
(DDRC) Write:
See page 309.
R
0
Reset:
Read:
0
0
0
0
0
0
Data Direction Register D
DDRD7 DDRD6 DDRD5 DDRD4 DDRD3 DDR2 DDRD1 DDRD0
(DDRD) Write:
See page 312.
Reset:
Read:
0
0
0
0
0
0
0
0
Port E Data Register
PTE7
PTE6
PTE5
PTE4
PTE3
PTE2
PTE1
PTE0
(PTE) Write:
See page 314.
Reset:
Unaffected by reset
PTF4 PTF3
Port F Data Register Read:
0
PTF6
PTF5
PTF2
PTF1
PTF0
(PTF)
See page 318.
Reset:
Write:
R
Unaffected by reset
= Reserved
= Unimplemented
R
U = Unaffected
Figure 2-2. Control, Status, and Data Registers (Sheet 1 of 9)
MC68HC908AS60 — Rev. 1.0
Technical Data
Memory Map
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