Freescale Semiconductor, Inc.
Analog-to-Digital Converter
A/D converter power-up and clock select
After enabling the A/D power, at least 100µs should be allowed for
system stabilization.
CSEL — Clock select
1 = A/D and EEPROM use internal RC clock source (about
1.5MHz).
0 = A/D and EEPROM use system E clock (must be at least 1MHz).
Selects alternate clock source for on-chip EEPROM and A/D charge
pumps. The on-chip RC clock should be used when the E clock
frequency falls below 1MHz.
IRQE — Configure IRQ for falling edge sensitive operation (refer to
Operating Modes and On-Chip Memory)
1 = Falling edge sensitive operation.
0 = Low level sensitive operation.
DLY — Enable oscillator start-up delay
1 = A delay of approximately 4000 E clock cycles is imposed as the
MCU is started up from the STOP mode.
0 = The oscillator start-up delay coming out of STOP is bypassed
and the MCU resumes processing within about four bus
cycles. A stable external oscillator is required if this option is
selected.
CME — Clock monitor enable (refer to Resets and Interrupts)
1 = Clock monitor enabled.
0 = Clock monitor disabled.
FCME — Force clock monitor enable (refer to Resets and Interrupts)
1 = Clock monitor enabled, cannot be disabled until next reset.
0 = Clock monitor follows the state of the CME bit.
CR[1:0] — COP timer rate select bits (refer to Resets and Interrupts)
MC68HC11P2 — Rev 1.0
Technical Data
Analog-to-Digital Converter
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