Freescale Semiconductor, Inc.
Analog-to-Digital Converter
An input voltage equal to VRL converts to $00 and an input voltage equal
to VRH converts to $FF (full scale), with no overflow indication. For
ratiometric conversions of this type, the source of each analog input
should use VRH as the supply voltage and be referenced to VRL.
9.4 A/D converter power-up and clock select
ADPU (bit 7 of the OPTION register) controls A/D converter power up.
Clearing ADPU removes power from and disables the A/D converter
system; setting ADPU enables the A/D converter system. After the A/D
converter is turned on, the analog bias voltages will take up to 100µs to
stabilize.
When the A/D converter system is operating from the MCU E clock, all
switching and comparator operations are synchronized to the MCU
clocks. This allows the comparator results to be sampled at ‘quiet’ times,
which minimizes noise errors. The internal RC oscillator is asynchronous
with respect to the MCU clock, so noise can affect the A/D converter
results. This results in a slightly lower typical accuracy when using the
internal oscillator (CSEL = 1).
9.4.1 OPTION — System configuration options register 1
State
on reset
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
System config. options 1
(OPTION)
$0039 ADPU CSEL IRQE DLY CME FCME CR1 CR0 0001 0000
The 8-bit special-purpose OPTION register sets internal system
configuration options during initialization. The time protected control bits,
IRQE, DLY, FCME and CR[1:0] can be written to only once in the first 64
cycles after a reset and then they become read-only bits. This minimizes
the possibility of any accidental changes to the system configuration.
They may be written at any time in special modes.
ADPU — A/D power-up
1 = A/D system power enabled.
Technical Data
MC68HC11P2 — Rev 1.0
Analog-to-Digital Converter
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