Freescale Semiconductor, Inc.
Analog-to-Digital Converter
Control, status and results registers
Channel select
control bits
Channel Result in ADRx
signal
if MULT = 1
CD:CC:CB:CA
0 0 0 0
AN0
AN1
ADR1
ADR2
ADR3
ADR4
ADR1
ADR2
ADR3
ADR4
—
0 0 0 1
0 0 1 0
AN2
0 0 1 1
AN3
0 1 0 0
AN4
0 1 0 1
AN5
0 1 1 0
AN6
0 1 1 1
AN7
1 0 X X
reserved
(1)
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
ADR1
ADR2
ADR3
ADR4
VRH
(1)
VRL
V
RH/2(1)
reserved(1)
1. Used for factory testing.
9.6.2 ADR1–ADR4 — A/D converter results registers
State
on reset
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
A/D result 1 (ADR1)
A/D result 2 (ADR2)
A/D result 3 (ADR3)
A/D result 4 (ADR4)
$0031 (bit 7) (6)
$0032 (bit 7) (6)
$0033 (bit 7) (6)
$0034 (bit 7) (6)
(5)
(5)
(5)
(5)
(4)
(4)
(4)
(4)
(3)
(3)
(3)
(3)
(2)
(2)
(2)
(2)
(1) (bit 0) undefined
(1) (bit 0) undefined
(1) (bit 0) undefined
(1) (bit 0) undefined
These read-only registers hold an 8-bit conversion result. Writes to these
registers have no effect. Data in the A/D converter result registers is valid
when the CCF flag in the ADCTL register is set, indicating a conversion
sequence is complete. If conversion results are needed sooner, refer to
Figure 9-3, which shows the A/D conversion sequence diagram.
MC68HC11P2 — Rev 1.0
Technical Data
Analog-to-Digital Converter
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