Freescale Semiconductor, Inc.
Analog-to-Digital Converter
Overview
9.3.5 A/D converter clocks
The CSEL bit in the OPTION register selects whether the A/D converter
uses the system E clock or an internal RC oscillator for synchronization.
When E clock frequency is below 750kHz, charge leakage in the
capacitor array can cause errors, and the internal oscillator should be
used. When the RC clock is used, additional errors can occur because
the comparator is sensitive to the additional system clock noise.
9.3.6 Conversion sequence
A/D converter operations are performed in sequences of four
conversions each. A conversion sequence can repeat continuously or
stop after one iteration. The conversion complete flag (CCF) is set after
the fourth conversion in a sequence to show the availability of data in the
result registers. Figure 9-3 shows the timing of a typical sequence.
Synchronization is referenced to the system E clock.
E clock
12 cycles
4 cycles 2 cyc 2 cyc 2 cyc 2 cyc 2 cyc 2 cyc 2 cyc 2 cyc
MSB bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
END
Sample analog input
Successive approximation sequence
Convert first
channel and
update ADR1
Convert second
Convert third
channel and
update ADR3
Convert fourth
channel and
update ADR4
channel and
update ADR2
0
32
64
96
128 E clock cycles
Figure 9-3. A/D conversion sequence
9.3.7 Conversion process
The A/D conversion sequence begins one E clock cycle after a write to
the A/D control/status register, ADCTL. The bits in ADCTL select the
MC68HC11P2 — Rev 1.0
Technical Data
Analog-to-Digital Converter
For More Information On This Product,
Go to: www.freescale.com
FREESCALE [ Freescale ]
