Freescale Semiconductor, Inc.
Timing System
maximum count, the counter rolls over to $0000, sets an overflow flag
and continues to increment. As long as the MCU is running in a normal
operating mode, there is no way to reset, change or interrupt the
counting. The capture/compare subsystem features three input capture
channels, four output compare channels and one channel that can be
selected to perform either input capture or output compare. Each of the
three input capture functions has its own 16-bit input capture register
(time capture latch) and each of the output compare functions has its
own 16-bit compare register. All timer functions, including the timer
overflow and RTI, have their own interrupt controls and separate
interrupt vectors.
The pulse accumulator contains an 8-bit counter and edge select logic.
The pulse accumulator can operate in either event counting mode or
gated time accumulation mode. During event counting mode, the pulse
accumulator’s 8-bit counter increments when a specified edge is
detected on an input signal. During gated time accumulation mode, an
internal clock source increments the 8-bit counter while an input signal
has a predetermined logic level.
The real-time interrupt (RTI) is a programmable periodic interrupt circuit
that permits pacing the execution of software routines by selecting one
of four interrupt rates.
The COP watchdog clock input (E/215) is tapped off from the free-
running counter chain. The COP automatically times out unless it is
serviced within a specific time by a program reset sequence. If the COP
is allowed to time out, a reset is generated, which drives the RESET pin
low to reset the MCU and the external system. Refer to Table 8-1 for
crystal related frequencies and periods.
Technical Data
MC68HC11P2 — Rev 1.0
Timing System
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