Freescale Semiconductor, Inc.
Serial Peripheral Interface (SPI)
7.7.2 SPSR — Serial peripheral status register
State
on reset
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
$0029 SPIF WCOL MODF
SPI status (SPSR)
0
0
0
0
0
0000 0000
SPIF — SPI interrupt complete flag
1 = Data transfer to external device has been completed.
0 = No valid completion of data transfer.
SPIF is set upon completion of data transfer between the processor
and the external device. If SPIF goes high, and if SPIE is set, a serial
peripheral interrupt is generated. To clear the SPIF bit, read the SPSR
with SPIF set, then access the SPDR. Unless SPSR is read (with
SPIF set) first, attempts to write SPDR are inhibited.
WCOL — Write collision
1 = Write collision.
0 = No write collision.
Clearing the WCOL bit is accomplished by reading the SPSR (with
WCOL set) followed by an access of SPDR. Refer to Slave select
and SPI system errors.
MODF — Mode fault
1 = Mode fault.
0 = No mode fault.
To clear the MODF bit, read the SPSR (with MODF set), then write to
the SPCR. Refer to Slave select and SPI system errors.
Bits [5, 3:0] — Not implemented; always read zero.
Technical Data
MC68HC11P2 — Rev 1.0
Serial Peripheral Interface (SPI)
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