Freescale Semiconductor, Inc.
Technical Data — MC68HC11P2
Section 8. Timing System
8.1 Contents
8.2
8.3
8.4
8.5
8.6
8.7
8.8
8.9
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137
Timer structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139
Input capture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .142
Output compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145
Real-time interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .154
Computer operating properly watchdog function. . . . . . .157
Pulse accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .158
Pulse-width modulation (PWM) timer . . . . . . . . . . . . . . . . .162
8.2 Introduction
The M68HC11 timing system is composed of five clock divider chains.
The main clock divider chain includes a 16-bit free-running counter,
which is driven by a programmable prescaler. The main timer’s
programmable prescaler provides one of the four clocking rates to drive
the 16-bit counter. Two prescaler control bits select the prescale rate.
The prescaler output divides the system clock by 1, 4, 8, or 16. Taps
from this main clocking chain drive circuitry generate the slower clocks
used by the pulse accumulator, the real-time interrupt (RTI), and the
computer operating properly (COP) watchdog subsystems, which are
also described in this section. Refer to Figure 8-1.
All main timer system activities are referenced to this free-running
MC68HC11P2 — Rev 1.0
Technical Data
Timing System
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