Freescale Semiconductor, Inc.
Timing System
Timer structure
TOI
TCNT (hi) TCNT (lo)
Prescaler
÷ 1, 4, 8, 16
PR[1:0]
9
&
MCU
TOF
16-bit
free running counter
E clock
Taps for RTI, COP and PA
†
Note
16-bit timer bus
To pulse accumulator
CFORC
OC1I
OC2I
OC3I
OC4I
I4/O5I
Force O/P
compare
8
7
6
5
4
&
+
16-bit comparator EQ
TOC1 (hi) TOC1 (lo)
PA7/
OC1F
OC2F
OC3F
OC1/
PAI
Bit 7
FOC1
FOC2
FOC3
FOC4
FOC5
&
+
16-bit comparator EQ
TOC2 (hi) TOC2 (lo)
PA6/
OC2/
OC1
Bit 6
Bit 5
Bit 4
&
+
16-bit comparator EQ
TOC3 (hi) TOC3 (lo)
PA5/
OC3/
OC1
&
+
16-bit comparator EQ
TOC4 (hi) TOC4 (lo)
OC4F
OC5
PA4/
OC4/
OC1
&
+
16-bit comparator EQ
PA3/
OC5/
OC1/
IC4
I4/O5F
IC4
TI4/O5 (hi) TI4/O5 (lo)
Bit 3
Bit 2
CLK
16-bit latch
IC1I
IC2I
IC3I
I4/O5
3
2
1
&
&
&
PA2/
IC1
CLK
IC1F
IC2F
IC3F
16-bit latch
TIC1 (hi) TIC1 (lo)
PA1/
IC2
CLK
Bit 1
16-bit latch
TIC2 (hi) TIC2 (lo)
PA0/
IC3
CLK
Bit 0
16-bit latch
TIC3 (hi) TIC3 (lo)
TFLG1
status
flags
TMSK1
interrupt
enables
Port A
pin
Pins/
functions
‡
control
† Interrupt requests 1–9 (these are further qualified by the I-bit in the CCR)
‡ Port A pin actions are controlled by OC1M, OC1D, PACTL, TCTL1 and TCTL2 registers
MC68HC11P2 — Rev 1.0
Technical Data
Timing System
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