Freescale Semiconductor, Inc.
Serial Peripheral Interface (SPI)
SPI registers
7.7.3 SPDR — SPI data register
State
on reset
Address bit 7
bit 6 bit 5
(5)
bit 4
(4)
bit 3 bit 2
(3) (2)
bit 1 bit 0
(1) (bit 0)
not
affected
SPI data (SPDR)
$002A (bit 7) (6)
The SPDR is used when transmitting or receiving data on the serial bus.
Only a write to this register initiates transmission or reception of a byte,
and this only occurs in the master device. At the completion of
transferring a byte of data, the SPIF status bit is set in both the master
and slave devices.
A read of the SPDR is actually a read of a buffer. To prevent an overrun
and the loss of the byte that caused the overrun, the first SPIF must be
cleared by the time a second transfer of data from the shift register to the
read buffer is initiated.
SPI is double buffered in and single buffered out.
7.7.4 OPT2 — System configuration options register 2
State
on reset
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
STRC
H
System config. options 2 (OPT2) $0038 LIRDV CWOM
IRVNE LSBF SPR2
0
0
000x 0000
LIRDV — LIR driven (refer to Operating Modes and On-Chip Memory)
1 = Enable LIR drive high pulse.
0 = LIR only driven low – requires pull-up on pin.
CWOM — Port C wired-OR mode (refer to Parallel Input/Output)
1 = Port C outputs are open-drain.
0 = Port C operates normally.
STRCH — Stretch external accesses (refer to Operating Modes and
On-Chip Memory)
1 = Off-chip accesses are extended by one E clock cycle.
0 = Normal operation.
MC68HC11P2 — Rev 1.0
Technical Data
Serial Peripheral Interface (SPI)
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