Freescale Semiconductor, Inc.
Serial Peripheral Interface (SPI)
IRVNE — Internal read visibility/not E (refer to Operating Modes and
On-Chip Memory)
1 = Data from internal reads is driven out of the external data bus.
0 = No visibility of internal reads on external bus.
In single chip mode this bit determines whether the E clock drives
out from the chip.
1 = E pin is driven low.
0 = E clock is driven out from the chip.
LSBF — LSB first enable
1 = Data is transferred LSB first.
0 = Data is transferred MSB first.
If this bit is set, data, which is usually transferred MSB first, is
transferred LSB first. LSBF does not affect the position of the MSB
and LSB in the data register. Reads and writes of the data register
always have MSB in bit 7.
SPR2 — SPI clock rate select
When set, SPR2 adds a divide-by-4 prescaler to the SPI clock chain.
With the two bits in the SPCR, this bit specifies the SPI clock rate.
Refer to Table 7-1.
Bits 1, 0 — not implemented; always read zero.
Technical Data
MC68HC11P2 — Rev 1.0
Serial Peripheral Interface (SPI)
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