Freescale Semiconductor, Inc.
Serial Peripheral Interface (SPI)
SPI registers
MSTR — Master mode select
1 = Master mode
0 = Slave mode
CPOL — Clock polarity
1 = SCK is active low.
0 = SCK is active high.
When the clock polarity bit is cleared and data is not being
transferred, the SCK pin of the master device has a steady state low
value. When CPOL is set, SCK idles high. Refer to Figure 7-2 and
Clock phase and polarity controls.
CPHA — Clock phase
The clock phase bit, in conjunction with the CPOL bit, controls the
clock-data relationship between master and slave. The CPHA bit
selects one of two different clocking protocols. Refer to Figure 7-2
and Clock phase and polarity controls.
SPR1 and SPR0 — SPI clock rate selects
These two bits select the SPI clock rate, as shown in Table 7-1. Note
that SPR2 is located in the OPT2 register and its state on reset is
zero.
Table 7-1. SPI clock rates
SPI clock frequency (≡ baud rate) for:
E clock
divide ratio
SPR[2:0]
E = 2MHz
1.0 MHz
500 kHz
125 kHz
62.5 kHz
250 kHz
125 kHz
31.3 kHz
15.6 kHz
E = 3MHz
1.5 MHz
750kHz
E = 4MHz
2.0 MHz
1.0 MHz
250 kHz
125 kHz
500 kHz
250 kHz
62.5 kHz
31.3 kHz
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
2
4
16
32
8
187.5 kHz
93.7 kHz
375 kHz
187.5 kHz
46.9 kHz
23.4 kHz
16
64
128
MC68HC11P2 — Rev 1.0
Technical Data
Serial Peripheral Interface (SPI)
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