Freescale Semiconductor, Inc.
Serial Peripheral Interface (SPI)
7.7 SPI registers
The three SPI registers, SPCR, SPSR, and SPDR, provide control,
status, and data storage functions. Refer to the following information for
a description of how these registers are organized.
7.7.1 SPCR — Serial peripheral control register
State
on reset
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
SPI control (SPCR)
$0028 SPIE SPE DWOM MSTR CPOL CPHA SPR1 SPR0 0000 01uu
SPIE — Serial peripheral interrupt enable
1 = A hardware interrupt sequence is requested each time SPIF or
MODF is set.
0 = SPI interrupts are inhibited.
Set the SPIE bit to a one to request a hardware interrupt sequence
each time the SPIF or MODF status flag is set. SPI interrupts are
inhibited if this bit is clear or if the I bit in the condition code register is
one.
SPE — Serial peripheral system enable
1 = Port D [5:2] is dedicated to the SPI.
0 = Port D has its default I/O functions.
When the SPE bit is set, the port D pins 2, 3, 4, and 5 are dedicated
to the SPI functions and lose their general purpose I/O functions.
When the SPI system is enabled and expects any of PD[4:2] to be
inputs then those pins will be inputs regardless of the state of the
associated DDRD bits. If any of PD[4:2] are expected to be outputs
then those pins will be outputs only if the associated DDRD bits are
set. However, if the SPI is in the master mode, DDD5 determines
whether PD5 is an error detect input (DDD5 = 0) or a general-purpose
output (DDD5 = 1).
DWOM — Port D wired-OR mode
1 = Port D [5:2] buffers configured for open-drain outputs.
0 = Port D [5:2] buffers configured for normal CMOS outputs.
Technical Data
MC68HC11P2 — Rev 1.0
Serial Peripheral Interface (SPI)
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