Freescale Semiconductor, Inc.
Serial Peripheral Interface (SPI)
SPI system errors
master, there is a chance of contention between two pin drivers. For
push-pull CMOS drivers, this contention can cause permanent damage.
The mode fault detection circuitry attempts to protect the device by
disabling the drivers. The MSTR control bit in the SPCR and all four
DDRD control bits associated with the SPI are cleared and an interrupt
is generated (subject to masking by the SPIE control bit and the I bit in
the CCR).
Other precautions may need to be taken to prevent driver damage. If two
devices are made masters at the same time, the mode fault detector
does not help protect either one unless one of them selects the other as
slave. The amount of damage possible depends on the length of time
both devices attempt to act as master.
A write collision error occurs if the SPDR is written while a transfer is in
progress. Because the SPDR is not double buffered in the transmit
direction, writes to SPDR cause data to be written directly into the SPI
shift register. Because this write corrupts any transfer in progress, a
write collision error is generated. The transfer continues undisturbed,
and the write data that caused the error is not written to the shifter.
A write collision is normally a slave error because a slave has no control
over when a master initiates a transfer. A master knows when a transfer
is in progress, so there is no reason for a master to generate a write-
collision error, although the SPI logic can detect write collisions in both
master and slave devices.
The SPI configuration determines the characteristics of a transfer in
progress. For a master, a transfer begins when data is written to SPDR
and ends when SPIF is set. For a slave with CPHA equal to zero, a
transfer starts when SS goes low and ends when SS returns high. In this
case, SPIF is set at the middle of the eighth SCK cycle when data is
transferred from the shifter to the parallel data register, but the transfer
is still in progress until SS goes high. For a slave with CPHA equal to
one, transfer begins when the SCK line goes to its active level, which is
the edge at the beginning of the first SCK cycle. The transfer ends when
SPIF is set, for a slave in which CPHA=1.
MC68HC11P2 — Rev 1.0
Technical Data
Serial Peripheral Interface (SPI)
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