Freescale Semiconductor, Inc.
Serial Peripheral Interface (SPI)
SPI signals
7.5 SPI signals
The following paragraphs contain descriptions of the four SPI signals:
master in slave out (MISO), master out slave in (MOSI), serial clock
(SCK), and slave select (SS).
Any SPI output line must have its corresponding data direction bit in
DDRD register set. If the DDR bit is clear, that line is disconnected from
the SPI logic and becomes a general-purpose input. All SPI input lines
are forced to act as inputs regardless of the state of the corresponding
DDR bits in DDRD register.
7.5.1 Master in slave out
MISO is one of two unidirectional serial data signals. It is an input to a
master device and an output from a slave device. The MISO line of a
slave device is placed in the high-impedance state if the slave device is
not selected.
7.5.2 Master out slave in
The MOSI line is the second of the two unidirectional serial data signals.
It is an output from a master device and an input to a slave device. The
master device places data on the MOSI line a half-cycle before the clock
edge that the slave device uses to latch the data.
7.5.3 Serial clock
SCK, an input to a slave device, is generated by the master device and
synchronizes data movement in and out of the device through the MOSI
and MISO lines. Master and slave devices are capable of exchanging a
byte of information during a sequence of eight clock cycles.
There are four possible timing relationships that can be chosen by using
control bits CPOL and CPHA in the serial peripheral control register
(SPCR). Both master and slave devices must operate with the same
MC68HC11P2 — Rev 1.0
Technical Data
Serial Peripheral Interface (SPI)
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