Freescale Semiconductor, Inc.
Serial Peripheral Interface (SPI)
SCK cycle #
(for reference)
1
2
3
4
5
6
7
8
SCK (CPOL=0)
SCK (CPOL=1)
Sample input
Data out (CPHA=0)
MSB
6
5
4
3
2
1
LSB
Sample input
Data out (CPHA=1)
MSB
6
5
4
3
2
1
LSB
SS (to slave)
Note: this figure shows the LSBF=0 (default) case. If LSBF=1, data is transferred in the reverse order (LSB first).
Figure 7-2. SPI transfer format
7.4.1 Clock phase and polarity controls
Software can select one of four combinations of serial clock phase and
polarity using two bits in the SPI control register (SPCR). The clock
polarity is specified by the CPOL control bit, which selects an active high
or active low clock, and has no significant effect on the transfer format.
The clock phase (CPHA) control bit selects one of two different transfer
formats. The clock phase and polarity should be identical for the master
SPI device and the communicating slave device. In some cases, the
phase and polarity are changed between transfers to allow a master
device to communicate with peripheral slaves having different
requirements.
When CPHA equals zero, the SS line must be deasserted and
reasserted between each successive serial byte. Also, if the slave writes
data to the SPI data register (SPDR) while SS is low, a write collision
error results.
When CPHA equals one, the SS line can remain low between
Technical Data
MC68HC11P2 — Rev 1.0
Serial Peripheral Interface (SPI)
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